In order to increase the operation speed of a computer system such as a microcontroller, for example, the speed of access to a memory needs to be increased. Memory interleaving is known as a technique of increasing the speed of access to a memory in a system. Based on this memory interleaving technique, a memory having consecutive addresses is divided into a plurality of memories, and the consecutive addresses are accessed in parallel. In this way, the apparent access time can be shortened. In such memory interleaving, if addresses of memory data requested by a single access from the CPU are always included in an address range accessible in parallel, simply divided memories are sufficient. However, if the requested addresses are not completely included in such address range, complex control, such as allocation of an incremented or decremented address to each of the divided memories, is required.
Patent Documents 1 to 4 disclose techniques of acquiring such misaligned data (data having an initial address that does not fall within an address range accessible by a single access) in a single bus cycle. Based on any one of the techniques disclosed in Patent Documents 1 to 4, a memory is divided into a plurality of memories for separately storing upper bits and lower bits, and an address conversion unit for allocating an incremented (or decremented) address to each of the divided memories is included. In this way, since different addresses are given to the upper and lower bit memories, misaligned data can be accessed at once.
On the other hand, FIG. 1 of Patent Document 5 discloses a storage device capable of accessing misaligned data at once, without dividing the memory or including the address conversion unit as disclosed in the above Patent Documents 1 to 4. Compared with Patent Documents 1 to 4, Patent Document 5 uses a simpler configuration to realize equivalent functions. Particularly, since there is no need to divide the memory, a read circuit or a write circuit does not need to be arranged for each of the divided memories. Thus, the storage device according to Patent Document 5 can suitably be formed on a single chip.
According to Patent Document 5, a 1-bit memory cell of a word (i) is connected to two word lines (i) and (i+1) and two bit lines. The two bit lines are used to read/write data when the word lines (i) and (i+1) are selected, respectively. In addition, the word line (i) is shared with memory cells of a word (i−1) and the word line (i+1) is shared with memory cells of a word (i+1). Based on this configuration, by selecting a single word line, memory cells of two consecutive words are selected, and by selecting an upper bit line or a lower bit line, a different address can be selected. Thus, misaligned data can be accessed at once.
Patent Document 1:
    Japanese Patent Kokai Publication No. JP-H03-44748APatent Document 2:    Japanese Patent Kokai Publication No. JP-H04-359334APatent Document 3:    Japanese Patent Kokai Publication No. JP-H05-73406APatent Document 4:    Japanese Patent Kokai Publication No. JP-H05-127985APatent Document 5:    Japanese Patent Kokai Publication No. JP-S63-308783A